Design of a Efficient Hybrid Adder using QCA

Authors:RAVI CHANDER, P.MURALI KRISHNA

0681-0684

Area Efficient Built-In Self Repair Analyzer with Ameliorated Repair Rate for Word-Oriented Memories

Authors:M.SHRAVANTI, T.VENU GOPAL, V.SIDDHARTHA

0685-0690

Area Efficient Pipelined Radix-2k Feedforward FFT Architectures using Booth Multiplier

Authors:JAMPA SHRAVANI, K.SIVA NAGI REDDY

0691-0698

Design and Analysis of Blow Fish and AES algorithm using VHDL

Authors:A. USHA KIRAN, MOHD JAVEED MEHD

0699-0702

Performance Evaluation of FIR Filter using Faithfully Truncated Multiplier

Authors:V.MALLIKARJUNA RAO, VENKATARAMANAIAH ANALAPUDI

0703-0708

Ship Monitoring using FPGA Design

Authors:ASMA BEGUM, B.SANDHYA, K.ASHOK BABU

0709-0713

Design and Implementation of 11:2 Compressors for Fast Addition

Authors:T.RAJYALAKSHMI, Y.RAVIKIRAN VARMA

0714-0721

High Speed Area Efficient Comparator using Parallel Prefix Structure

Authors:V.G.MAHENDRA KUMAR, Y.MAMATHA

0722-0728

An Adaptive Design Approach to Achieve Fault Coverage in Sequential Circuits

Authors:PRANAY HANUMANDLA, CH.RAMESH

0729-0733

The Adaptive Bus Systems with Half Duplex Voice Communication by Zigbee & AM Signal as a Communication Medium

Authors:KOPPULA MANASA, J.VAMSHI KRISHNA

0734-0740